As semiconductor device technology has progressed, the device geometries have shrunk. Decreasing the geometries have increased the density of the devices, reduced the cost of the devices, while increasing the speed of the devices. However, as oxide layer thickness are decreased the electric field per unit area increases significantly for a given supply voltage. Meanwhile, the breakdown-voltage for the dielectric remains relatively the same. As a result it has become necessary to reduce the maximum junction breakdown voltage for integrated semiconductor devices. However, the power supply voltage and/or the input/output levels (determined by specifications, standards, protocols, and the like) typically lag behind by one generation.
For example, an integrated semiconductor device may be fabricated such that the maximum source-to-gate, drain-to-gate, and drain-to-source junction voltage cannot exceed 2.75V. However, the supply voltage provided to the device is 3.3V. Thus, if the supply voltage appears across a junction of a device, the device could be damaged.
In the conventional art, electronic devices are also often replaced. For example a card may go bad and need to be replaced with another card, or an older card may need to be upgraded to a newer card. Typically, replacing electronic devices requires powering down the system to which it is attached prior to removing old devices and/or installing the new device. However, powering down the system results in the entire system not being available for use while a device providing a particular function is removed and or installed.
Referring to FIG. 1A, a circuit diagram of a simplified input/output stage, and FIG. 1B a cross-sectional view of the physical layout thereof, according to the conventional art is shown. As depicted in FIG. 1A, the I/O stage comprises a pull-up element MP1 and a pull-down element MN2. The pull-down element MN2 is an n-type metal-oxide-semiconductor field effect transistor (MOSFET), having a source and body coupled to Vss (e.g., a ground terminal), a gate coupled to a pull-down control signal path (AN), and a drain coupled to an input/output terminal (PAD). The pull-up element MP1 is a p-type MOSFET having a source and well coupled to Vdd (e.g., a supply terminal), a gate coupled to a pull-up control signal path (AP), and a drain coupled to the PAD.
During normal conditions, the PAD can be driven high in response to a low signal on AP and AN. The PAD can also be driven low in response to a high signal on AP and AN. Furthermore, the PAD can be driven to a tristate state condition in response to a high signal on AP and a low signal on AN.
During live-insertion conditions, the voltage on the supply, pull-up control signal and pull-down control signal paths are effectively at ground. Therefore, MP1 will be on and provide a current path to Vdd. In such a case, if the current is not limited the drain-well junction will be damaged resulting in failure of the device. When Vpad exceeds a diode drop, a conducting path 130 is also created from the drain of MP1 to the supply terminal, as illustrated in FIG. 1B. If the current is not limited the drain-well junction will be damaged resulting in failure of the device. Furthermore, if Vpad exceeds the breakdown voltage of the gate oxide layer 110120, the gate oxide layer 110, 120 for either MP1 or MN2 will be damaged resulting in failure of the device.
Accordingly, it is desirable for semiconductor device to protect against junction breakdown due to over-voltage conditions. It is also desirable to be able to remove and/or install subsystems (e.g., replacing one card with another card) without affecting the normal operation of the system (e.g., without powering down the computer).